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16k x16/18 synchronous dual port static ram cy7c09269a cy7c09369a cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-06050 rev. ** revised september 19, 2001 25/0251 features ? true dual-ported memory cells which allow simulta- neous access of the same memory location two flow-through/pipelined devices ? 16k x 16/18 organization (cy7c09269a/369a) three modes ? flow-through ? pipelined ?burst pipelined output mode on both ports allows fast 100- mhz cycle time 0.35-micron cmos for optimum speed/power high-speed clock to data access 6.5 [1] /7.5/9/12 ns (max.) low operating power ? active = 195 ma (typical) ? standby = 0.05 ma (typical) fully synchronous interface for easier operation burst counters increment addresses internally ? shorten cycle times ? minimize bus noise ? supported in flow-through and pipelined modes dual chip enables for easy depth expansion upper and lower byte controls for bus matching automatic power-down commercial temperature range available in 100-pin tqfp pin-compatible and functionally equivalent to idt709269 notes: 1. see page 6 for load conditions. 2. i/o 8 ? i/o 15 for x16 devices; i/o 9 ? i/o 17 for x18 devices. 3. i/o 0 ? i/o 7 for x16 devices. i/o 0 ? i/o 8 for x18 devices. logic block diagram r/w l 1 0 0/1 ce 0l ce 1l lb l oe l ub l 1b 0/1 0b 1a 0a ba ft /pipe l i/o 8/9l ? i/o 15/17l i/o 0l ? i/o 7/8l i/o control counter/ address register decode a 0l ? a 13l clk l ads l cnten l cntrst l true dual-ported ram array r/w r 1 0 0/1 ce 0r ce 1r lb r oe r ub r 1b 0/1 0b 1a 0a b a ft /pipe r i/o control counter/ address register decode 14 8/9 8/9 i/o 8/9r ? i/o 15/17r i/o 0r ? i/o 7/8r a 0r ? a 13r clk r ads r cnten r cntrst r 14 8/9 8/9 [2] [3] [2] [3] for the most recent information, visit the cypress web site at www.cypress.com
cy7c09269a cy7c09369a document #: 38-06050 rev. ** page 2 of 17 functional description the cy7c09269a and cy7c09369a are high-speed synchro- nous cmos 16k, 32k, and 64k x 16/18 dual-port static rams. two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. [4] reg- isters on control, address, and data lines allow for minimal set- up and hold times. in pipelined output mode, data is registered for decreased cycle time. clock to data valid t cd2 = 6.5 ns [1] (pipelined). flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. in flow-through mode data will be available t cd1 = 15 ns after the address is clocked into the device. pipelined output or flow- through mode is selected via the ft /pipe pin. each port contains a burst counter on the input address regis- ter. the internal write pulse width is independent of the low- to-high transition of the clock signal. the internal write pulse is self-timed to allow the shortest possible cycle times. a high on ce 0 or low on ce 1 for one clock cycle will power down the internal circuitry to reduce the static power consump- tion. the use of multiple chip enables allows easier banking of multiple chips for depth expansion configurations. in the pipelined mode, one cycle is required with ce 0 low and ce 1 high to reactivate the outputs. counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. a port ? s burst counter is loaded with the port ? s address strobe (ads ). when the port ? s count enable (cnten ) is asserted, the address counter will increment on each low-to-high transition of that port ? s clock signal. this will read/write one word from/into each successive address location until cnten is deasserted. the counter can address the entire memory array and will loop back to the start. counter reset (cntrst ) is used to reset the burst counter. all parts are available in 100-pin thin quad plastic flatpack (tqfp) packages. pin configurations notes: 4. when writing simultaneously to the same location, the final value cannot be guaranteed. 5. for cy7c09269a pin #18 connected to v cc is equivalent to an idt x16 pipelined device; connecting pin #18 and #58 to gnd is equivalent to an idt x16 flow- through device. 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 a9r a10r a11r a12r a13r nc ubr nc lbr ce1r cntrstr oer ft /piper nc nc gnd r/wr gnd i/o15r i/o14r i/o13r i/o12r i/o11r i/o10r ce0r 58 57 56 55 54 53 52 51 a9l a10l a11l a12l a13l nc ubl nc lbl ce1l cntrstl oel ft /pipel nc nc vcc r/wl gnd i/o15l i/o14l i/o13l i/o12l i/o11l i/o10l ce0l 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 a8l a7l a6l a5l a4l a3l clkl a1l cntenl gnd adsr a0r a1r a0l a2l clkr cntenr a2r a3r a4r a5r a6r a7r a8r adsl 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 nc i/o9r i/o8r i/o7r vcc i/o6r i/01r i/o4r i/o2r gnd i/o0l i/o2l i/o3l i/o3r i/o5r i/o1l gnd i/o4l i/o5l i/o6l i/o7l vcc i/o8l i/o9l i/o0r 33 32 31 30 29 28 27 26 100-pin tqfp (top view) [5] [5] cy7c09269a (16k x 16)
cy7c09269a cy7c09369a document #: 38-06050 rev. ** page 3 of 17 pin configurations (continued) selection guide cy7c09269a cy7c09369a -6 [1] cy7c09269a cy7c09369a -7 cy7c09269a cy7c09369a -9 cy7c09269a cy7c09369a -12 f max2 (mhz) (pipelined) 100 83 67 50 max access time (ns) (clock to data, pipelined) 6.5 7.5 9 12 typical operating current i cc (ma) 250 235 215 195 typical standby current for i sb1 (ma) (both ports ttl level) 45 40 35 30 typical standby current for i sb3 (ma) (both ports cmos level) 0.05 0.05 0.05 0.05 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 a8r a9r a10r a11r a12r a13r ce0r nc ubr cntrstr r/wr ft /piper i/o17r lbr nc gnd oer gnd i/o16r i/o15r i/o14r i/o13r i/o12r i/o11r ce1r 58 57 56 55 54 53 52 51 a9l a10l a11l a12l a13l nc ce1l lbl ce0l r/wl oel i/o17l i/o16l ubl nc vcc ft /pipel gnd i/o15l i/o14l i/o13l 1/012l i/o11l i/o10l cntrstl 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 a8l a7l a6l a5l a4l a3l clkl a1l cntenl gnd gnd cntenr a0r a0l a2l adsr clkr a1r a2r a3r a4r a5r a6r a7r adsl 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 i/10r i/o9r i/o8r i/o7r vcc i/o6r i/01r i/o4r i/o2r gnd i/o0l i/o2l i/o3l i/o3r i/o5r i/o1l gnd i/o4l i/o5l i/o6l i/o7l vcc i/o8l i/o9l i/o0r 33 32 31 30 29 28 27 26 100-pin tqfp (top view) cy7c09369a (16k x 18)
cy7c09269a cy7c09369a document #: 38-06050 rev. ** page 4 of 17 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied .. ? 55 c to +125 c supply voltage to ground potential ............... ? 0.3v to +7.0v dc voltage applied to outputs in high z state ................................. ? 0.5v to +7.0v dc input voltage............................................ ? 0.5v to +7.0v output current into outputs (low)............................. 20 ma static discharge voltage ........................................... >1100v latch-up current..................................................... >200 ma pin definitions left port right port description a 0l ? a 13l a 0r ? a 13r address inputs. ads l ads r address strobe input. used as an address qualifier. this signal should be asserted low to access the part using an externally supplied address. asserting this signal low also loads the burst counter with the address present on the address pins. ce 0l ,ce 1l ce 0r ,ce 1r chip enable input. to select either the left or right port, both ce 0 and ce 1 must be asserted to their active states (ce 0 v il and ce 1 v ih ). clk l clk r clock signal. this input can be free running or strobed. maximum clock input rate is f max . cnten l cnten r counter enable input. asserting this signal low increments the burst address counter of its respective port on each rising edge of clk. cnten is disabled if ads or cntrst are asserted low. cntrst l cntrst r counter reset input. asserting this signal low resets the burst address counter of its respec- tive port to zero. cntrst is not disabled by asserting ads or cnten . i/o 0l ? i/o 17l i/o 0r ? i/o 17r data bus input/output (i/o 0 ? i/o 15 for x16 devices). lb l lb r lower byte select input. asserting this signal low enables read and write operations to the lower byte. (i/o 0 ? i/o 8 for x18, i/o 0 ? i/o 7 for x16) of the memory array. for read operations both the lb and oe signals must be asserted to drive output data on the lower byte of the data pins. ub l ub r upper byte select input. same function as lb , but to the upper byte (i/o 8/9l ? i/o 15/17l ). oe l oe r output enable input. this signal must be asserted low to enable the i/o data pins during read operations. r/w l r/w r read/write enable input. this signal is asserted low to write to the dual port memory array. for read operations, assert this pin high. ft /pipe l ft /pipe r flow-through/pipelined select input. for flow-through mode operation, assert this pin low. for pipelined mode operation, assert this pin high. gnd ground input. nc no connect. v cc power input. operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10%
cy7c09269a cy7c09369a document #: 38-06050 rev. ** page 5 of 17 note: 6. ce l and ce r are internal signals. to select either the left or right port, both ce 0 and ce 1 must be asserted to their active states (ce 0 v il and ce 1 v ih ). electrical characteristics over the operating range parameter description cy7c09269a cy7c09369a unit -6 [1] -7 -9 -12 min. typ. max. min. typ. max. min. typ. max. min. typ. max. v oh output high voltage (v cc = min., i oh = ? 4.0 ma) 2.42.42.42.4 v v ol output low voltage (v cc = min., i oh = +4.0 ma) 0.40.40.40.4v v ih input high voltage 2.2 2.2 2.2 2.2 v v il input low voltage 0.8 0.8 0.8 0.8 v i oz output leakage current ? 10 10 ? 10 10 ? 10 10 ? 10 10 a i cc operating current (v cc =max., i out =0ma) outputs disabled com ? l. 250 450 235 420 215 360 195 300 ma i sb1 standby current (both ports ttl level) [6] ce l & ce r v ih , f=f max com ? l. 45 115 40 105 35 95 30 85 ma i sb2 standby current (one port ttl level) [6] ce l | ce r v ih , f = f max com ? l. 175 235 160 220 145 205 125 190 ma i sb3 standby current (both ports cmos level) [6] ce l & ce r v cc ? 0.2v, f = 0 com ? l. 0.05 0.5 0.05 0.5 0.05 0.5 0.05 0.5 ma i sb4 standby current (one port cmos level) [6] ce l | ce r v ih , f=f max com ? l. 160 200 145 185 130 170 110 150 ma capacitance parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 10 pf c out output capacitance 10 pf
cy7c09269a cy7c09369a document #: 38-06050 rev. ** page 6 of 17 ac test loads (applicable to -6 only) [7] note: 7. test conditions: c = 10 pf. ac test loads (a) normal load (load 1) r1 = 893 ? 5v output r2 = 347 ? c= 30 pf v th =1.4v output c= 30 pf (b) th venin equivalent (load 1) (c) three-state delay (load 2) r1 = 893 ? r2 = 347 ? 5v output c= 5pf r th = 250 ? (used for t cklz , t olz , & t ohz including scope and jig) v th =1.4v output c (a) load 1 (-6 only) r = 50 ? z 0 = 50 ? 3.0v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses 0.00 0. 1 0 0.20 0.30 0.40 0.50 0.60 1 0 1 5 20 25 30 35 (b) load derating curve capacitance (pf) ? (ns) for all -12 access times
cy7c09269a cy7c09369a document #: 38-06050 rev. ** page 7 of 17 notes: 8. test conditions used are load 2. 9. this parameter is guaranteed by design, but it is not production tested. switching characteristics over the operating range parameter description cy7c09269a cy7c09369a unit -6 [1] -7 -9 -12 min. max. min. max. min. max. min. max. f max1 f max flow-through 53 45 40 33 mhz f max2 f max pipelined 100 83 67 50 mhz t cyc1 clock cycle time - flow-through 19 22 25 30 ns t cyc2 clock cycle time - pipelined 10 12 15 20 ns t ch1 clock high time - flow-through 6.5 7.5 12 12 ns t cl1 clock low time - flow-through 6.5 7.5 12 12 ns t ch2 clock high time - pipelined 4568ns t cl2 clock low time - pipelined 4568ns t r clock rise time 3333ns t f clock fall time 3333ns t sa address set-up time 3.5 4 4 4 ns t ha address hold time 0011ns t sc chip enable set-up time 3.5 4 4 4 ns t hc chip enable hold time 0011ns t sw r/w set-up time 3.5 4 4 4 ns t hw r/w hold time 0011ns t sd input data set-up time 3.5 4 4 4 ns t hd input data hold time 0011ns t sad ads set-up time 3.5 4 4 4 ns t had ads hold time 0011ns t scn cnten set-up time 3.5444ns t hcn cnten hold time 0011ns t srst cntrst set-up time 3.5 4 4 4 ns t hrst cntrst hold time 0011ns t oe output enable to data valid 8 9 10 12 ns t olz [8, 9] oe to low z 2222ns t oz [8, 9] oe to high z 17171717ns t cd1 clock to data valid - flow-through 15 18 20 25 ns t cd2 clock to data valid - pipelined 6.5 7.5 9 12 ns t dc data output hold after clock high2222ns t ckhz [8, 9] clock high to output high z 29292929ns t cklz [8, 9] clock high to output low z 2222ns port to port delays t cwdd write port clock high to read data delay 30 35 40 40 ns t ccs clock to clock set-up time 9 10 15 15 ns
cy7c09269a cy7c09369a document #: 38-06050 rev. ** page 8 of 17 switching waveforms read cycle for flow-through output (ft /pipe = v il ) [10, 11, 12, 13] read cycle for pipelined operation (ft /pipe = v ih ) [10, 11, 12, 13] notes: 10. oe is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 11. ads = v il , cnten and cntrst = v ih . 12. the output is disabled (high-impedance state) by ce 0 =v ih or ce 1 = v il following the next rising edge of the clock. 13. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only. t ch1 t cl1 t cyc1 t sc t hc t dc t ohz t oe t sc t hc t sw t hw t sa t ha t cd1 t ckhz t dc t olz t cklz a n a n+1 a n+2 a n+3 q n q n+1 q n+2 clk ce 0 ce 1 r/w address data out oe t ch2 t cl2 t cyc2 t sc t hc t sw t hw t sa t ha a n a n+1 clk ce 0 ce 1 r/w address data out oe a n+2 a n+3 t sc t hc t ohz t oe t olz t dc t cd2 t cklz q n q n+1 q n+2 1 latency
cy7c09269a cy7c09369a document #: 38-06050 rev. ** page 9 of 17 bank select pipelined read [14, 15] left port write to flow-through right port read [16, 17, 18, 19] notes: 14. in this depth expansion example, b1 represents bank #1 and b2 is bank #2; each bank consists of one cypress dual-port device from this data sheet. address (b1) = address (b2) . 15. ub , lb , oe and ads = v il ; ce 1(b1) , ce 1(b2) , r/w , cnten , and cntrst = v ih . 16. the same waveforms apply for a right port write to flow-through left port read. 17. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and cntrst = v ih . 18. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 19. it t ccs maximum specified, then data from right port read is not valid until the maximum specified for t cwdd . if t ccs >maximum specified, then data is not valid until t ccs + t cd1 . t cwdd does not apply in this case. switching waveforms (continued) d 3 d 1 d 0 d 2 a 0 a 1 a 2 a 3 a 4 a 5 d 4 a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha t sc t hc t sa t ha t sc t hc t sc t hc t sc t hc t ckhz t dc t dc t cd2 t cklz t cd2 t cd2 t ckhz t cklz t cd2 t ckhz t cklz t cd2 t ch2 t cl2 t cyc2 clk l address (b1) ce 0(b1) data out(b2) data out(b1) address (b2) ce 0(b2) t sa t ha t sw t hw t sd t hd match valid t ccs t sw t hw t dc t cwdd t cd1 match t sa t ha match no match no valid valid t dc t cd1 clk l r/w l address l data inl address r data outr clk r r/w r
cy7c09269a cy7c09369a document #: 38-06050 rev. ** page 10 of 17 pipelined read-to-write-to-read (oe = v il ) [13, 20, 21, 22] pipelined read-to-write-to-read (oe controlled) [13, 20, 21, 22] notes: 20. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 21. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . 22. during ? no operation, ? data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa t hw t sw t cd2 t ckhz t sd t hd t cklz t cd2 no operation write read read clk ce 0 ce 1 r/w address data in data out a n a n+1 a n+2 a n+2 d n+2 a n+3 a n+4 q n q n+3 t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa a n a n+1 a n+2 a n+3 a n+4 a n+5 t hw t sw t sd t hd d n+2 t cd2 t ohz read read write d n+3 t cklz t cd2 q n q n+4 clk ce 0 ce 1 r/w address data in data out oe
cy7c09269a cy7c09369a document #: 38-06050 rev. ** page 11 of 17 flow-through read-to-write-to-read (oe = v il ) [11, 13, 20, 21] flow-through read-to-write-to-read (oe controlled) [11, 13, 20, 21] switching waveforms (continued) t ch1 t cl1 t cyc1 t sc t hc t sw t hw t sa t ha t sw t hw t sd t hd a n a n+1 a n+2 a n+2 a n+3 a n+4 d n+2 q n q n+1 q n+3 t cd1 t cd1 t dc t ckhz t cd1 t cd1 t cklz t dc read no operation write read clk ce 0 ce 1 address r/w data in data out q n t ch1 t cl1 t cyc1 t sc t hc t sw t hw t sa t ha t cd1 t dc t ohz read a n a n+1 a n+2 a n+3 a n+4 a n+5 d n+2 d n+3 t sw t hw t sd t hd t cd1 t cd1 t cklz t dc q n+4 t oe write read clk ce 0 ce 1 address r/w data in data out oe
cy7c09269a cy7c09369a document #: 38-06050 rev. ** page 12 of 17 pipelined read with address counter advance [23] flow-through read with address counter advance [23] note: 23. ce 0 and oe = v il ; ce 1 , r/w and cntrst = v ih . switching waveforms (continued) counter hold read with counter t sa t ha t sad t had t scn t hcn t ch2 t cl2 t cyc2 t sad t had t scn t hcn q x-1 q x q n q n+1 q n+2 q n+3 t dc t cd2 read with counter read external address clk address ads data out cnten a n t ch1 t cl1 t cyc1 t sa t ha t sad t had t scn t hcn q x q n q n+1 q n+2 q n+3 a n t sad t had t scn t hcn t dc t cd1 counter hold read with counter read external address read with counter clk address ads data out cnten
cy7c09269a cy7c09369a document #: 38-06050 rev. ** page 13 of 17 write with address counter advance (flow-through or pipelined outputs) [24, 25] notes: 24. ce 0 , ub , lb , and r/w = v il ; ce 1 and cntrst = v ih . 25. the ? internal address ? is equal to the ? external address ? when ads = v il and equals the counter output when ads = v ih . switching waveforms (continued) t ch2 t cl2 t cyc2 a n a n+1 a n+2 a n+3 a n+4 d n+1 d n+1 d n+2 d n+3 d n+4 a n d n t sad t had t scn t hcn t sd t hd write external write with counter address write with counter write counter hold clk address internal cnten ads data in address t sa t ha
cy7c09269a cy7c09369a document #: 38-06050 rev. ** page 14 of 17 counter reset (pipelined outputs) [13, 25, 26, 27] notes: 26. ce 0 , ub , and lb = v il ; ce 1 = v ih . 27. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset. switching waveforms (continued) t ch2 t cl2 t cyc2 clk address internal cnten ads data in address cntrst r/w data out q 0 q 1 q n d 0 a x 01a n a n+1 t sad t had t scn t hcn t srst t hrst t sd t hd t sw t hw a n a n+1 t sa t ha counter reset write address 0 read address 0 read address 1 read address n
cy7c09269a cy7c09369a document #: 38-06050 rev. ** page 15 of 17 notes: 28. ? x ? = ? don ? t care, ? ? h ? = v ih , ? l ? = v il . 29. ads , cnten , cntrst = ? don ? t care. ? 30. oe is an asynchronous input signal. 31. when ce changes state in the pipelined mode, deselection and read happen in the following clock cycle. 32. ce 0 and oe = v il ; ce 1 and r/w = v ih . 33. data shown for flow-through mode; pipelined mode output will be delayed by one cycle. 34. counter operation is independent of ce 0 and ce 1 . read/write and enable operation [28, 29, 30] inputs outputs oe clk ce 0 ce 1 r/w i/o 0 ? i/o 17 operation x h x x high-z deselected [31] x x l x high-z deselected [31] x l h l d in write l l h h d out read [34] h x l h x high-z outputs disabled address counter control operation [28, 32, 33, 34] address previous address clk ads cnten cntrst i/o mode operation x x x x l d out(0) reset counter reset to address 0 a n x l x h d out(n) load address load into counter x a n h h h d out(n) hold external address blocked ? counter disabled x a n h l h d out(n+1) increment counter enabled ? internal address generation
cy7c09269a cy7c09369a document #: 38-06050 rev. ** page 16 of 17 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. ordering information 16k x16 synchronous dual-port sram speed (ns) ordering code package name package type operating range 6.5 [1] cy7c09269a-6ac a100 100-pin thin quad flat pack commercial 7.5 cy7c09269a-7ac a100 100-pin thin quad flat pack commercial 9 cy7c09269a-9ac a100 100-pin thin quad flat pack commercial 12 cy7c09269a-12ac a100 100-pin thin quad flat pack commercial 16k x18 synchronous dual-port sram speed (ns) ordering code package name package type operating range 6.5 [1] cy7c09369a-6ac a100 100-pin thin quad flat pack commercial 7.5 CY7C09369A-7AC a100 100-pin thin quad flat pack commercial 9 cy7c09369a-9ac a100 100-pin thin quad flat pack commercial 12 cy7c09369a-12ac a100 100-pin thin quad flat pack commercial package diagram 100-pin thin plastic quad flat pack (tqfp) a100 51-85048-b
cy7c09269a cy7c09369a document #: 38-06050 rev. ** page 17 of 17 document title: cy7c09269a/cy7c09369a 16k x 16/18 synchronous dual port static ram document number: 38-06050 rev. ecn no. issue date orig. of change description of change ** 110202 11/11/01 szv change from spec number: 38-00836 to 38-06050

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